Investigation into voltage and process variation-aware manufacturing test

Increasing integration and complexity in IC design provides challenges for manufacturing testing. This thesis studies how process and supply voltage variation influence defect behaviour to determine the impact on manufacturing test cost and quality. The focus is on logic testing of static CMOS designs with respect to two important defect types in deep submicron CMOS: resistive bridges and full opens. The first part of the thesis addresses testing for resistive bridge defects in designs with multiple supply voltage settings. To enable analysis, a fault simulator is developed using a supply voltage-aware model for bridge defect behaviour. The analysis shows that for high defect coverage it is necessary to perform test for more than one supply voltage setting, due to supply voltage-dependent behaviour. A low-cost and effective test method is presented consisting of multi-voltage test generation that achieves high defect coverage and test set size reduction without compromise to defect coverage. Experiments on synthesised benchmarks with realistic bridge locations validate the proposed method.The second part focuses on the behaviour of full open defects under supply voltage variation. The aim is to determine the appropriate value of supply voltage to use when testing. Two models are considered for the behaviour of full open defects with and without gate tunnelling leakage influence. Analysis of the supply voltage-dependent behaviour of full open defects is performed to determine if it is required to test using more than one supply voltage to detect all full open defects. Experiments on synthesised benchmarks using an extended version of the fault simulator tool mentioned above, measure the quantitative impact of supply voltage variation on defect coverage.The final part studies the impact of process variation on the behaviour of bridge defects. Detailed analysis using synthesised ISCAS benchmarks and realistic bridge model shows that process variation leads to additional faults. If process variation is not considered in test generation, the test will fail to detect some of these faults, which leads to test escapes. A novel metric to quantify the impact of process variation on test quality is employed in the development of a new test generation tool, which achieves high bridge defect coverage. The method achieves a user-specified test quality with test sets which are smaller than test sets generated without consideration of process variation

Variation aware analysis of bridging fault testing

This paper investigates the impact of process variation on test quality with regard to resistive bridging faults. The input logic threshold voltage and gate drive strength parameters are analyzed regarding their process variation induced influence on test quality. The impact of process variation on test quality is studied in terms of test escapes and measured by a robustness metric. It is shown that some bridges are sensitive to process variation in terms of logic behavior, but such variation does not necessarily compromise test quality if the test has high robustness. Experimental results of Monte-Carlo simulation based on recent process variation statistics are presented for ISCAS85 and -89 benchmark circuits, using a 45nm gate library and realistic bridges. The results show that tests generated without consideration of process variation are inadequate in terms of test quality, particularly for small test sets. On the other hand, larger test sets detect more of the logic faults introduced by process variation and have higher test quality

Level of confidence evaluation and its usage for Roll-back Recovery with Checkpointing optimization

Increasing soft error rates for semiconductor devices manu- factured in later technologies enforces the use of fault tolerant techniques such as Roll-back Recovery with Checkpointing (RRC). However, RRC introduces time overhead that increases the completion (execution) time. For non-real-time systems, research have focused on optimizing RRC and shown that it is possible to find the optimal number of checkpoints such that the average execution time is minimal. While minimal average execution time is important, it is for real-time systems important to provide a high probability that deadlines are met. Hence, there is a need of probabilistic guarantees that jobs employing RRC complete before a given deadline. First, we present a mathematical framework for the evaluation of level of confidence, the probability that a given deadline is met, when RRC is employed. Second, we present an optimization method for RRC that finds the number of checkpoints that results in the minimal completion time while the minimal com- pletion time satisfies a given level of confidence requirement. Third, we use the proposed framework to evaluate probabilistic guarantees for RRC optimization in non-real-time systems

Bridging fault test method with adaptive power management awareness

A key design constraint of circuits used in handheld devices is the power consumption, mainly due to battery life limitations. Adaptive power management (APM) techniques aim to increase the battery life of such devices by adjusting the supply voltage and operating frequency, and thus the power consumption, according to the workload. Testing for resistive bridging defects in APM-enabled designs raises a number of challenges due to their complex analog behavior. Testing at more than one supply voltage setting can be employed to improve defect coverage in such systems, however, switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes a multi-Vdd automatic test generation method which delivers 100% resistive bridging defect coverage and also a way of reducing the number of supply voltage settings required during test through test point insertion. The proposed techniques have been experimentally validated using a number of benchmark circuits

Process variation-aware test for resistive bridges

This paper analyses the behaviour of resistive bridging faults under process variation and shows that process variation has a detrimental impact on test quality in the form of test escapes. To quantify this impact, a novel metric called test robustness is proposed and to mitigate test escapes, a new process variation-aware test generation method is presented. The method exploits the observation that logic faults that have high probability of occurrence and correspond to significant amounts of undetected bridge resistance have a high impact on test robustness and therefore should be targeted by test generation. Using synthesised ISCAS benchmarks with realistic bridge locations, results show that for all the benchmarks, the method achieves better results (less test escapes) than tests generated without consideration of process variatio

Ethical dilemmas and their solving in social work micro practice

Diplomdarba tēmas nosaukums ir „Ētiskās dilemmas un to risināšana sociālā darba mikro praksē”. Diplomdarba mērķis ir teorētiski un empīriski pētīt un analizēt ētikas dilemmas un to risināšanu sociālā darba mikro praksē. Diplomdarba ietvaros teorētiskajā daļā ir apskatīti tādi jautājumi kā sociālā darba mikro prakse, ētikas un vērtību jēdziens sociālā darba mikro praksē, ētiskās dilemmas sociālā darba mikro praksē. Darba pamatā liela uzmanība pievērsta tieši ētiskām dilemmām un to risināšanas veidiem, kā arī plašāk analizētas sociālā darba mikro prakses vērtības un ētika. Lai sasniegtu darba mērķi, autores veica empīrisko pētījumu, lai noskaidrotu, kā sociālie darbinieki risina ētiskas dilemmas un, kādas ir visbiežāk sastopamās ētiskās dilemmas sociālā darba mikro praksē. Tika noskaidrots kādas metodes sociālie darbinieki izmanto un vai ir informēti par teorētiskajām vadlīnijām ētisko dilemmu risināšanā sociālā darba mikro praksē. Pamatojoties uz iegūtajiem pētījuma rezultātiem, ir izstrādāti secinājumi un ieteikumi efektīvākas ētisko dilemmu risināšanas veicināšanai sociālā darba mikro praksē. Izstrādātie ieteikumi var palīdzēt un atvieglot sociālo darbinieku darbu ētisko dilemmu lēmumu pieņemšanā. Atslēgvārdi: ētiskās dilemmas, mikro prakse, vērtības, ētika.The subject of the Bachelor's Paper is Ethical dilemmas and their solving in social work micro practise. The aim of the Paper is to study and analyze theoretically and empirically ethic dilemmas and solving them in social work micro practice. The theoretical part of the Paper overlooks such aspects as social work micro practice, ethic dilemmas in social work, the notion of ethic and values in social work micro practice, ethic dilemmas and the ways of solving them, as well as a wide analysis of values and ethics at social work micro practice. In order to reach the aim of the Paper the authors conducted an empiric research to find out the way social workers solve ethic dilemmas and the kinds of the most frequent ethic dilemmas in social work micro practice. The authors found out the methods social workers apply and whether they are informed about the theoretical directions in solving ethic dilemmas in social work micro practice. Taking into consideration the results of the research the authors worked out conclusions and recommendations to further solving ethic dilemmas in social work micro practice. The recommendations been worked out are possible to help in solving ethic dilemmas in social work. Key words: ethic dilemmas, micro practice, values, ethics

Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias

Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSV-SICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost